The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor technologies further advance, stacked IC devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked IC device, active circuits such as logic, memory, processor circuits and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers are then positioned on top of one another to form a stacked IC. For example, two semiconductor wafers may be bonded together through suitable bonding techniques, and thereafter assembled into a single stacked IC device. One advantage of a stacked IC device is that high density can be achieved. Although existing stacked IC devices and methods of fabricating stacked IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Improvements in this area are desired.